1. Field of the Invention
The present invention relates to a semiconductor storage device and a high-speed address-latching method that are compatible with a high-speed DDR (Double Data Rate) system, for example, LPDDR2 (Low Power DDR2).
Priority is claimed on Japanese Patent Application No. 2007-265418, filed Oct. 11, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, semiconductor storage devices have required both low power consumption and high speed operation, and thereby required the high access efficiency of each signal. For example, DRAM compliant with LPDDR2 specifications has been required.
As a high-speed address-latching system in the DDR system, a function of sharing input pins for an address signal and a command signal that have been conventionally separated and a function of fetching a command and an address on rising and falling edges of a clock signal are under consideration.
In a conventional general DDR circuit as shown in FIG. 9A, command data and address data are fetched in synchronism with only a rising edge R1 of a clock signal CK (with a period of tCK) in the case of an ACTV (activation) command, for example.
As shown in FIG. 9B, an edge-trigger-type latch circuit 20 is used as the latch circuit for fetching command data and address data. As a result, an access time is determined by a trigger signal generated based on the rising edge R1 of the clock signal CK.
Since data are fetched both on rising and falling edges in the high-speed system, access penalty of a period ½ tCK occurs as shown in FIG. 10 if the edge-trigger-type latch circuit 20 shown in FIG. 9B is used. In other words, an address access time t1 is determined based on a falling edge F1, and an access time t2 from the rising edge R1 increases by ½ tCK compared with the access time t1.
For this reason, the problem of the access penalty of the period ½ tCK has been required to be solved in the DDR high-speed address-fetching system in which the input pins for the address signal and the command signal are shared and command data and address data are fetched both on rising and falling edges.
A memory control method and a memory control circuit are disclosed in Japanese Unexamined Patent Application, Fast Publication No. 2003-76602 as the conventional technique related to the present invention. However, an object of the memory control method and the memory control circuit of conventional techniques is to propose a memory control circuit that enables flexible and easy post-adjustment without much load on memory design and difficulty in dedicate timing adjustment, and not to solve the problem of the access penalty of the period ½ tCK in the DDR high-speed system.